High-speed LAN technologies include 100BASE-T (Fast Ethernet), 1000BASE-T (Gigabit Ethernet), and 10GBASE-T. These high-speed LAN technologies include link partner transceivers that can communicate, for example, over a bi-directional transmission channel. An exemplary transmission channel includes four pairs of copper wire.
Proper operation of the Ethernet link partners requires them to be synchronized. Synchronization can be obtained by one link partner phase-locking a clock to data signals transmitted by the other link partner. The transmitter and receiver processing of one of the transceiver link partners are clocked by the phase-locked clock. For Ethernet systems, data signals can be distorted during link establishment. In addition, external noise can be added onto the data signals, that can add excessive jitter to the phase-locked clock or cause the clock to lose phase-lock. Too much jitter on the clock signals can introduce excessive errors to the transmission and/or reception of data signals between the transceiver link partners.
A master transceiver can monitor a phase error signal of signals received from a slave transceiver link partner. Therefore, the phase error provides an indication of the quality of the phase-lock of the slave transceiver link partner. This, however, is undesirable because the master transceiver is required to support the error detection circuitry, and the phase-lock status detection happens with a time delay after the slave transceiver link partner loses phase-lock. If detected, the first transceiver can drop the link with the second transceiver link partner, or stop adaptation of processing of data signals received from the second transceiver link partner.
It is desirable to have a system, apparatus and method of aiding synchronization between Ethernet transceiver link partners. It is desirable that the method and apparatus operate efficiently, and not require excessive amounts of additionally electronic circuitry.